1. Field of the Invention
The present invention is related generally to a circuit in a personal computer or in a peripheral device for collecting data scattered in a number of locations in a system memory of the personal computer via a first bus (also called "computer bus"), and in particular to such a circuit for refetching of the collected data after flushing of the collected data during an initial transmission on a second bus (also called "peripheral bus") to which are coupled a number of peripheral devices.
2. Description of the Related Art
A personal computer 90 (FIG. 1A) includes a plug-in board 10 that is coupled to two buses namely (1) a computer bus (such as the ISA/EISA bus well known in the art) 20 on a mother board 60 and (2) a peripheral bus (e.g. SCSI bus also well known in the art) 40. Peripheral bus 40 is, in turn, connected to one or more peripheral devices, e.g. devices 31 and 32. Similarly, computer bus 20 is coupled to one or more devices on board 60, such as system memory 64, and to a local bus 65 that in turn is coupled to a host processor 61 (e.g. the microprocessor PENTIUM available from Intel Corporation, Santa Clara, Calif.). Local bus 65 is also coupled to a read only memory (also called "processor ROM") 62 that holds software, e.g. Basic Input-Output System (BIOS) instructions to be executed by processor 61 on power up. Moreover, plug-in board 10 also includes a read only memory 11 that is programmed with instructions to be executed by host adapter 12 on power up. Instead of being mounted on a separate board 10, host adapter 12 and read only memory 11 can be mounted directly on a mother board 70 (FIG. 1B).
Peripheral bus 40 may conform to the specification of the Small Computer System Interface (SCSI) standard avail able from the American National Standards Institute (ANSI x3.131-1986) of 1430 Broadway, New York, N.Y. 10018. The just-described SCSI standard specification is incorporated by reference herein in its entirety. Additional descriptions related to the SCSI bus may be found in, for example, U.S. Pat. Nos. 4,864,291 and 4,905,184 that are both incorporated by reference herein in their entirety.
Computer bus 20 may conform to any of the computer bus standards, such as the Industry Standard Architecture (ISA), Extended ISA (EISA), or Peripheral Component Interconnect (PCI). The PCI specification is available from PCI Special Interest Group (SIG), M/S HF3-15A, 5200 NE Elam Young Parkway, Hillsborough, Oreg. 97124-6497, phone number 503/696-2000, and is incorporated by reference herein in its entirety. Additional descriptions related to the PCI bus can be found in the book "PCI System Architecture", Second Edition, by Tom Shanley and Don Anderson, MindShare Press, Richardson, Tex., 1994 also incorporated by reference herein in its entirety.
Computer bus 20 is typically faster than peripheral bus 40, and therefore a conventional host adapter 12 (as described in, for example, U.S. Pat. No. 5,659,690 by Stuber et al that is incorporated by reference herein in its entirety) has FIFO buffers to store data temporarily during passage between peripheral bus 40, and computer bus 20. Host adapter 12 can transfer the data between peripheral device 31 and system memory 64, without intervention of host processor 61, in a mechanism known as "Direct Memory Access" (DMA), as described by Stuber et al at column 90, line 38 et seq.
The data transfer described above can be initiated by transferring to host adapter 12 a command in the form of a "Sequencer Control Block" (SCB) that contains information needed by host adapter 12 to perform the data transfer, as described by Stuber et al. at column 17, line 66 et. seq. Moreover, host adapter 12 can transfer the data to/from system memory 64 via a scatter/gather mechanism that stores the data in a number of portions in system memory 64. The SCB includes "a pointer to a scatter/gather data transfer pointer list, [and] a count of the number of elements in the scatter/gather list" (column 18, lines 3-5) that together indicate the portions of system memory 64 (FIG. 1A) to or from which the data is to be transferred.
Host adapter 12 typically has more than one SCSI command pending in a queue of SCBs as described by Stuber et al. at column 20, line 1 et seq. In one example, SCBs for each of two peripheral devices 31 and 32 are queued, and when a first peripheral device 31 disconnects from host adapter 12 (e.g. while the drive mechanics are repositioned) host adapter 12 communicates with a second peripheral device 32 to execute an SCSI command indicated by the another SCB. The ability of host adapter 12 to switch back and forth between SCBs, is referred to as "context switching" (Stuber et al., column 20, line 9).
A context switch (e.g. when a data transfer is suspended or is completed) is not performed if host adapter 12 encounters an unexpected event (such as an error) during transmission of data that was prefetched. When host adapter 12 encounters an error, host adapter 12 may suspend the data transfer to allow peripheral bus 40 to be used by others. At this time, host adapter 12 holds data in the above-described FIFO buffer that was prefetched. Until the FIFO buffer is emptied, e.g. by transmission of the prefetched data, host adapter 12 cannot use peripheral bus 40 for another data transfer (using another SCB). To recover from an error, host adapter 12 maintains the data in the FIFO buffer and tries (e.g. periodically) to retransmit the prefetched data, until the data is successfully transferred or is flushed. Host adapter 12 flushes the data when a device on peripheral bus 40 indicates that the device is sending data that must be placed in the FIFO buffer. When host adapter 12 flushes the data, adapter 12 returns an error status for the command being executed by the data transfer, so that the software driver in memory 64 later re-issues the command to adapter 12.